As the density of fast, static MOS random access memories (RAMs) continues to increase, it has become increasingly difficult to use the standard sense amplifier designs used in less dense memory devices. The use of smaller memory cells and the use of common data out lines coupled to bit lines by selected transfer devices have reduced the differential signal available for sensing. Furthermore, with increasing density, the current drawn by the prior art sense amplifiers has become more critical.
Referring to FIG. 1, there is shown the basic schematic of a differential sense amplifier used in many static RAM (random access memory) devices. To focus attention on the relevant features, the precharge circuitry has been left off. However, it may be noted that prior to sensing, node SE is low and nodes IN and INB are precharged to a high level, typically V.sub.cc or V.sub.cc -.vertline.V.sub.t .vertline., where V.sub.cc is the power supply voltage and V.sub.t is the threshold of the transistors being used.
During a memory access cycle, a differential signal is generated by a memory cell on IN and INB, and SE goes high to cause the sense amplifier to sense or amplify the input signal.
The sense amplifier shown in FIG. 1 has several problems which become more important as memory density increases. First, the sense amplifier consumes d.c. power when SE is high because all of the devices in the sense amplifier are on. In other words, .vertline.V.sub.GS .vertline.&gt;.vertline.V.sub.t .vertline. for all of the transistors in the sense amplifier. To reduce the power consumed, the device sizes must be reduced, which increases the response time and the output drive of the circuit.
Second, if device M5 is not sufficiently large, devices M2, M4 and M5 will act as a voltage divider (i.e., the sense amplifier will have poor gain). As a result, the output voltage on node N2 cannot reach either V.sub.cc or V.sub.ss. Thus, a buffer inverter is often added to "square up" the output of the sense amplifier.
Finally, the sense amplifier in FIG. 1 only has a single output, which in some applications is not desirable for driving output circuits.
Referring to FIGS. 2 and 3, there are shown two additional prior art sense amplifier designs, using two or more stages to provide differential outputs. The differential input signal required to produce a large output voltage swing in these sense amplifiers is typically 0.5 volts unless additional stages are added to the sense amplifier. However, in fast SRAMs (static RAMs), the time to develop such a large differential signal from the selected memory cell is usually costly in terms of speed or die size. A typical SRAM develops a differential signal at 50 millivolts per nanosecond. Therefore it can take 10 nanoseconds before there is enough signal on the bit lines (or common data out lines) to enable the sense amplifier to reliably sense the input signal.
The present invention provides a dynamic sense amplifier with the following features, which provide improved performance and reliability. First, the sense amplifier draws no d.c. current after latching, and which can reliably sense and latch very small voltage differentials (typically 50 to 100 millivolts is sufficient) at very high speeds. The present invention accomplishes this by using a circuit that has a very low intrinsic load (i.e., on the internal nodes of the device), and by using dynamic circuitry to reduce the power consumed. The fast latching provided by the sense amplifier improves its noise immunity by reducing the amount of time during which sensing is performed. The present invention also uses a circuit configuration which reduces its sensitivity to transistor gain nonuniformities compared to prior art sense amplifiers. Finally, the sense amplifier of the present invention uses a two stage amplifier in which the two stages simultaneously amplify the input signal, with the second stage coupled to the first so that it can be scaled or sized to drive relatively large loads without significantly slowing down the operation of the sense amplifier.